datasheet serial programmable triple pll ss versaclock synth i cs3 0 9 idt? serial programmable triple pll ss versaclock synth 1 ics309 rev l 091311 description the ics309 is a versatile se rially-programmable, triple pll with spread spectrum clock source. the ics309 can generate any frequency from 250khz to 200 mhz, and up to 6 different output frequencies simultaneously. the outputs can be reprog rammed on-the-fly, and will lock to a new frequency in 10 ms or less. to reduce system emi emi ssions, spread spectrum is available that supports modulation frequencies of 31 khz and 120 khz, as well as modulation amplitudes of +/-0.25% to +/-2.0%. both center and down-spread options are available. the device includes a pdts pin which tri-states the output clocks and powers down the entire chip. the ics309 default for non-programmed start-up are buffered reference clock outputs on all clock output pins. idt?s versaclock tm programming software allows the user to configure up to 9 outputs with target frequencies, spread spectrum capabilities or buffered reference clock outputs. the versaclock tm software automatically configures the plls for optimal overall performance. features packaged in 20-pin ssop (q sop) ? pb-free, rohs compliant highly accurate frequency generation m/n multiplier pll: m = 1..2048, n = 1..1024 serially programmable: user determines the output frequency via a 3-wire interface spread spectrum frequency modulation for reduced system emi center or down spread up to 4% total selectable 32 khz and 120 khz modulation eliminates need for custom quartz oscillators input crystal frequency of 5 - 27 mhz input clock frequency of 3 - 50 mhz output clock frequencies up to 200 mhz operating voltage of 3.3 v up to 9 reference clock outputs power down tri-state mode very low jitter block diagram crystal oscillator pll1 with spread spectrum gnd 2 3 vdd pdts pll2 pll3 divide logic and output enable control clk1 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 x2 crystal or clock input external capacitors are required with a crystal input. x1/iclk sclk data strobe
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 2 ics309 rev l 091311 pin assignment pin descriptions 16 1 15 2 14 data strobe 3 13 x2 4 12 x1/iclk sclk 5 11 clk9 6 pdts 7 vdd 8 gnd vdd vdd gnd clk1 clk5 clk2 clk6 9 10 clk3 clk7 clk4 clk8 2019 18 17 20 pin (150 mil) ssop (qsop) pin number pin name pin type pin description 1 data input serial data input. 2 x2 xo crystal output. connect this pin to a crystal. float for clock input. 3 x1/iclk xi connect this pin to a crystal or external clock input. 4 clk9 output output clock 9. default of re ference frequency output when unprogrammed. 5 vdd power connect to +3.3v. 6 gnd power connect to ground. 7 clk1 output output clock 1. default of re ference frequency output when unprogrammed. 8 clk2 output output clock 2. default of re ference frequency output when unprogrammed. 9 clk3 output output clock 3. default of re ference frequency output when unprogrammed. 10 clk4 output output clock 4. default of re ference frequency output when unprogrammed. 11 clk8 output output clock 8. default of re ference frequency output when unprogrammed. 12 clk7 output output clock 7. default of re ference frequency output when unprogrammed. 13 clk6 output output clock 6. default of re ference frequency output when unprogrammed. 14 clk5 output output clock 5. default of re ference frequency output when unprogrammed. 15 gnd power connect to ground. 16 vdd power connect to +3.3 v. 17 vdd power connect to +3.3 v. 18 pdts input powers down entire chip, tri-states all outputs when low. internal pull-up. 19 sclk input serial shift register clock. see timing diagram. 20 strobe input strobe to load data. see timing diagram. use external 250 kohm pull-up.
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 3 ics309 rev l 091311 configuring the ics309 initial state: the ics309 may be co nfigured to have up to 9 frequen cy outputs, utiliz ing the 4 on-board plls and spread spectrum circuitry. unprogrammed, the part has the following outputs, related to the reference input clock: the strobe pin must have an external 250 kohm pull-up resistor to acheive the initial state. the input crystal range for the ics309 is 5 mhz to 27 mhz. the ics309 can be programmed to set the output functions and frequencies. 160 data bits generated b y the versaclock tm software are written in data pin in this order: msb (left most bit) first. as show in figure 2, after thes e 160 bits are clocked into the ic s309, taking strobe high will send this data to the internal latch and th e clk output will lock within 10 ms. note : strobe utilizes a transparent latch t hat is latched when in the high state. if strobe is in the high state and sclk is pulsed, data is clocked directly to the internal latch and the output co nditions will change accordingly. alt hough this will not damage the ics309, it is recommended that strobe be kept low while data is being clocked into the ics309 in order to avoid unintended changes on the output clocks . all outputs may be turned off during initialization by bringing the pdts pin to ground. when pdts is brought high, after the st robe pin in brought high, the programmed ou tput frequencies will be available. ac parameters for writing to the ics309 default outputs output frequency clocks 1 - 9 (pins 4, 7-14) reference output parameter condition min. max. units t setup setup time 10 ns t hold hold time after sclk 10 ns t w data wait time 10 ns t s strobe pulse width 40 ns sclk frequency 30 mhz data t hold t setup sclk strobe t s t w figure 2. timing diagram for programming the ics309 bit160 bit2 bit1 bit3 bit159 bit158
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 4 ics309 rev l 091311 external components series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 . strobe pull-up resistor in order for the device to start up in the default state, a 250 kohm pull-up resistor is required. decoupling capacitors as with any high-performance mixed-signal ic, the ics309 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very shor t pcb traces (and no vias) been the crystal and device. crystal capacitors must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -6 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each crystal capacitor would be 20 pf [(16-6) x 2] = 20. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. 2) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi, the 33 series termination resistor (if needed) should be placed close to each clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. ics309 configurat ion capabilities the architecture of the ics309 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. the frequency multiplier pll provides a high degree of precision. the m/n values (the multiplier/divide values available to generate the target vco frequency) can be set within the range of m = 1 to 2048 and n = 1 to 1024. the ics309 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same pll. each output frequency can be represented as: output freq. = (ref. freq)*(m/n)/output divide idt versaclock software idt applies years of pll optimization experience into a user friendly software that accepts the user?s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. the user does not need to have prior pll experience or determine the optimal vco frequency to support multiple output frequencies. versaclock software quickly evaluates accessible vco frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. the user may evaluate output accuracy, performance trade-off scenarios in seconds.
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 5 ics309 rev l 091311 spread spectrum modulation the ics309 utilizes frequen cy modulation (fm) to distribute energy over a range of frequencies. by modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system?s electro-magnetic interference (emi). the modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. spread spectrum modulation can be applied as either ?center spread? or ?down spread?. during center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. the effective average frequency is equal to the target frequency. in applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. in this case, the maximum frequency, including modulation, is the target frequency. the effective average frequency is less than the target frequency. the ics309 operates in both center spread and down spread modes. for center spread, the frequency can be modulated between 0.125% to 2.0%. for down spread, the frequency can be modulated between -0.25% to -4.0%. both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common vco frequency can be identified. spread spectrum modulation rate the spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. for applications requiring the driving of ?down-circuit? plls, zero delay buffers, or those adhering to pci standards, the spread spectrum modulation rate should be set to 30-33 khz. for other applications, a 120 khz modulation option is available. absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics309. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functio nal operation of the device at these or any other conditions above those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions parameter condition min. typ. max. units supply voltage, vdd referenced to gnd 7 v inputs referenced to gnd -0.5 vdd+ 0.5 v clock outputs referenced to gnd -0.5 vdd+ 0.5 v storage temperature -65 150 c soldering temperature max 10 seconds 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c ambient operating temperature (ics309ri) -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +3.6 v power supply ramp time 4 ms
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 6 ics309 rev l 091311 dc electrical characteristics vdd=3.3 v 10% , ambient temperature -40 to +85 c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 3.00 3.60 v operating supply current input high voltage idd configuration dependent - see versaclock tm estimates ma ex. 25 mhz crystal, vdd=3.3v, no load, 9 - 33.3333 mhz outs, pdts = 1 25 ma pdts = 0 20 a input high voltage v ih x1/iclk only (vdd/2)+1 v input low voltage v il x1/iclk only (vdd/2)-1 v input high voltage v ih vdd-0.5 v input low voltage v il pdts , sclk, data, strobe 0.8 v output high voltage v oh i oh = -8 ma 2.4 v output low voltage v ol i ol = 8 ma 0.4 v output high voltage, cmos level v oh i oh = -4 ma vdd-0.4 v short circuit current clk outputs + 70 ma input capacitance c in pdts pin 4 pf internal pull-down resistor r pd clk outputs 525 k internal pull-up resistor r pu pdts pin 250 k
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 7 ics309 rev l 091311 ac electrical characteristics vdd = 3.3 v 10% , ambient temperature -40 to +85 c, unless stated otherwise note 1: measured with 15 pf load. note 2: duty cycle is configuration dependent. most configurations are min 45% / max 55% thermal characteristics parameter symbol conditions min. typ. max. units input frequency f in fundamental crystal 5 27 mhz input clock 2 50 mhz output frequency vdd=3.3 v 0.25 200 mhz output clock rise time t or 20% to 80%, note 1 0.8 ns output clock fall time t of 80% to 20%, note 1 0.8 ns output clock duty cycle note 2 40 49-51 60 % power-up time pdts goes high until stable clk output 41 0m s pdts goes high until stable clk out, spread spectrum off .2 2 ms pdts goes high until stable clk out, spread spectrum on 47m s maximum output jitter, short term t j reference clock 300 ps maximum output jitter, short term t j all other clocks, c l =15 pf configuration 200 ps pin-to-pin skew low skew outputs -250 250 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 135 c/w ja 1 m/s air flow 93 c/w ja 3 m/s air flow 78 c/w thermal resistance junction to case jc 60 c/w
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 8 ics309 rev l 091311 marking diagram (commercial) marking diagram (industrial) notes: 1. ?lot? is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?lf? denotes rohs compliant package. 4. ?i? denotes industrial temperature range. 5. bottom marking: country of origin if not usa. 309rlf lot yyww 309RILFlot yyww
ics309 serial programmable triple pll ss versaclock synth ser prog cloc k synthesizer idt? serial programmable triple pll ss versaclock synth 9 ics309 rev l 091311 package outline and package dimensions (20-pin ssop, 150 mil. wide body) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number denotes pb-free configuration, rohs compliant. while the information presented herein has been checked for bot h accuracy and reliability, integrated device technology (idt) assumes no responsibility for either its use or for the infringem ent of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature 309rlf see page 8 tubes 20-pin ssop 0 to +70 c 309rlft tape and reel 20-pin ssop 0 to +70 c 309RILF see page 8 tubes 20-pin ssop -40 to +85 c 309RILFt tape and reel 20-pin ssop -40 to +85 c indexarea 1 2 20 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 -- 1.50 -- 0.059 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 8.55 8.75 0.337 0.344 e 5.80 6.20 0.228 0.244 e1 3.80 4.00 0.150 0.157 e .635 basic .025 basic l 0.40 1.27 0.016 0.050 0 8 0 8 aaa -- 0.10 -- 0.004
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